www.lansdale.com page 1 of 5 issue 0 ml12040 phase frequency detector legacy device: motorola mc12040 the ml12040 is a phase?requency detector intended for use in systems requiring zero phase and frequency difference at lock. in combination with a voltage controlled oscillator (such as the ml12149), it is useful in a broad range of phase?ocked loop applications. ? operating frequency = 80 mhz typical ? operating temperature range t a = 0 to 75? pin connections v cc2 n.c. v cc1 (top view) n.c. u u n.c. r v ee d d n.c. v n.c. 1 2 3 4 14 13 12 11 5 6 7 10 9 8 pin conversion table 14 pin dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 pin plcc 2 3 4 6 8 9 10 12 13 14 16 18 19 20 0 0 1 0 r 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 v 1 1 1 0 1 0 1 0 1 1 1 x x x x u 1 1 1 1 0 0 0 0 0 0 0 x x x x d 0 0 0 0 0 0 1 1 1 1 0 x x x x u 0 0 0 0 1 1 1 1 1 1 1 x x x x d 1 1 1 1 1 1 0 0 0 0 1 inputs outputs logic diagram r s q s rq r 6 v 9 4 u (f r >f v ) 3 u (f r >f v ) 12 d (f v >f r ) 11 d (f v >f r ) v cc1 = pin 1 v cc2 = pin 14 v ee = pin 7 truth table this is not strictly a functional truth table; i.e., it does not cover all possible modes of operation. however, it gives a sufficient number of tests to ensure that the device will function properly in all modes of operation. plcc 20 = -4p plastic package case 775 3 19 4 8 14 1 p dip 14 = cp plastic package case 646 cross reference/ordering information motorola p dip 14 mc12040p ml12040cp plcc 20 mc12040fn ML12040-4P lan s dale package note : lansdale lead free ( p b ) product, as it becomes available, will be identified by a part number prefix change from ml to ml e .
lan s dale s emiconductor, inc. ml12040 www.lansdale.com page 2 of 5 issue 0 6 r 9v u4 d 12 d 11 u 3 test voltage values (volts) @ test temperature v ihmax v ilmin v ihamin v ilamax v ee 0 c ?.840 ?.870 ?.145 ?.490 ?.2 25 c ?.810 ?.850 ?.105 ?.475 ?.2 supply voltage = ?.2v 75 c ?.720 ?.830 ?.045 ?.450 ?.2 mc12040 test voltage applied to pins below pin under 0 c 25 c 75 c test voltage applied to pins below (v cc ) symbol characteristics u n d er test min max min max min max unit v ihmax v ilmin v ihamin v ilamax v ee (v cc ) gnd i e power supply drain 7 ?20 ?0 madc 7 1,14 i inh input current 6 9 350 350 adc 6 9 7 7 1,14 1,14 v oh 1 logic 1 output voltage 3 4 11 12 ?.000 ?.840 ?.960 ?.810 ?.900 ?.720 vdc 7 1,14 v ol 1 logic 0 output voltage 3 4 11 12 ?.870 ?.635 ?.850 ?.620 ?.830 ?.595 vdc 7 1,14 v oha 2 logic 1 input voltage 3 4 11 12 ?.020 ?.980 ?.920 vdc 6.9 7 1,14 v ola 2 logic 0 input voltage 3 4 11 12 ?.615 ?.600 ?.575 vdc 9 6 9 6 6 9 6 9 7 1,14 test voltage values (volts) @ test temperature v ihmax v ilmin v ihamin v ilamax v ee 0 c +4.160 +3.130 +3.855 +3.510 +5.0 25 c +4.190 +3.150 +3.895 +3.525 +5.0 supply voltage = +5.0v 75 c +4.280 +3.170 +3.955 +3.550 +5.0 mc12040 test voltage applied to pins below pin under 0 c 25 c 75 c test voltage applied to pins below (v cc ) symbol characteristics u n d er test min max min max min max unit v ihmax v ilmin v ihamin v ilamax v ee (v cc ) gnd i e power supply drain 7 ?15 ?0 madc 1,14 7 i inh input current 6 9 350 350 adc 6 9 1,14 1,14 7 7 v oh 1 logic 1 output voltage 3 4 11 12 4.000 4.160 4.040 4.190 4.100 4.280 vdc 1,14 7 v ol 1 logic 0 output voltage 3 4 11 12 3.190 3.430 3.210 3.440 3.230 3.470 vdc 1,14 7 v oha 2 logic 1 input voltage 3 4 11 12 3.980 4.020 4.080 vdc 6.9 1,14 7 v ola 2 logic 0 input voltage 3 4 11 12 3.450 3.460 3.490 vdc 9 6 9 6 6 9 6 9 1,14 7 electrical characteristics the ml12040 has been designed to meet the dc specifica- tions shown in the test table after thermal equilibrium has been established. outputs are terminated through a 50 resistor to 3.0 v for 5.0 v tests and through a 50 resistor to ?.0 v for ?.2 v tests. note : for more information on using an ecl device in a 5.0 v system, refer to application note an1406/d, ?esigning with pecl (ecl at 5.0 v)
lan s dale s emiconductor, inc. ml12040 www.lansdale.com page 3 of 5 issue 0 figure 1. ac tests notes: 1 all input and output cables to the scope are equal lengths of 50 coaxial cable. 2 unused input and outputs are connected to a 50 resistor to ground. 3 the device under test must be preconditioned before performing the ac tests. preconditioning may be accomplished by applying pulse generator 1 for a minimum of two pulses prior to pulse gen- erator 2. the device must be preconditioned again when inputs to pins 6 and 9 are interchanged. the same technique applies. 50% pulse gen 1 6 r 9 v u 4 d 12 d 11 u 3 pulse gen 1 pulse gen 2 p r f = 5.0 mhz duty cycle = 50% t+ = t?= 1.5 ns 0.2 ns to scope channel a to scope channel b 7 v ee = ?.2 or ?.0 v 0.1 f 5.0 f 0.1 f v cc = +2.0 v 1 14 pulse gen 2 output waveform a output waveform b 50% 50% 50% 10% 90% 10% 90% 80% 20% 20% 80% 1.1 v 1.1 v 0.3 v 0.3 v t+ t t+ t t+ t t t+ 20ns t+ t++ t++ t+ ml12040 test voltages/waveforms 0 c 25 c 85 c applied to pins listed symbol characteristic pin under test output waveform max max max unit pulse gen 1 pulse gen 2 v ee ?.0 or ?.2 v v cc 2.0 v t 6+4+ t 6+12+ t 6+3 t 6+11 t 9+11+ t 9+3+ t 9+12 t 9+4 propagation delay 6,4 6,12 6,3 6,11 9,11 9,3 9,12 9,4 b a a b b a a b 4.6 6.0 4.5 6.4 4.6 6.0 4.5 6.4 4.6 6.0 4.5 6.4 4.6 6.0 4.5 6.4 5.0 6.6 4.9 7.0 5.0 6.6 4.9 7.0 ns 6 9 6 9 9 6 9 6 9 6 9 6 6 9 6 9 7 1,14 t 3+ t 4+ t 11+ t 14+ output rise time 3 4 11 14 a b b a 3.4 3.4 3.8 ns 6 6 9 9 9 9 6 6 7 1,14 t 3 t 4 t 11 t 14 output fall time 3 4 11 14 a b b a 3.4 3.4 3.8 ns 6 6 9 9 9 9 6 6 7 1,14
lan s dale s emiconductor, inc. ml12040 www.lansdale.com page 4 of 5 issue 0 the ml12040 is a logic network designed for use as a phase comparator for mecl?ompatible input signals. it determines the ?ead?or ?ag?phase relationship and the time difference between the leading edges of the waveforms. since these edges occur only once per cycle, the detector has a range of 2 radians. operation of the device may be illustrated by assuming two waveforms, r and v (figure 2), of the same frequency but dif- fering in phase. if the logic had established by past history that r was leading v, the u output of the detector (pin 4) would produce a positive pulse width equal to the phase difference and the d output (pin 11 ) would simply remain low. on the other hand, it is also possible that v was leading r (figure 2), giving rise to a positive pulse on the d output and a constant low level on the u output pin. both outputs for the sample condition are valid since the determination of lead or lag is dependent on past edge crossing and initial conditions at start?p. a stable phase?ocked loop will result from either condition. phase error information is contained in the output duty cycle that is, the ratio of the output pulse width to total period. by inte- grating or low pass filtering the outputs of the detector and shift- ing the level to accommodate ecl swings, usable analog infor- mation for the voltage controlled oscillator can be developed. a circuit useful for this function is shown in figure 3. proper level shifting is accomplished by differentially driving the operational amplifier from the normally high outputs of the phase detector (u and d). using this technique the quiescent differential voltage to the operational amplifier is zero (assum- ing matched ??levels from the phase detector). the u and d outputs are then used to pass along phase information to the operational amplifier. phase error summing is accomplished through resistors r1 connected to the inputs of the operational amplifier. some r? filtering imbedded within the input net- work (figure 3) may be very beneficial since the very narrow correctional pulses of the ml12040 would not normally be integrated by the amplifier. phase detector gain for this config- uration is approximately 0.16 volts/radian. system phase error stems from input offset voltage in the operational amplifier, mismatching of nominally equal resis- tors, and mismatching of phase detector ?igh?states between the outputs used for threshold setting and phase measuring. all these effects are reflected in the gain constant. for example, a 16 mv offset voltage in the amplifier would cause an error of 0.016/0.16 = 0.1 radian or 5.7 degrees of error. phase error can be trimmed to zero initially by trimming either input offset or one of the threshold resistors (r1 in figure 3). phase error over temperature depends on how much the offending parame- ters drift. legacy applications information figure 2. timing diagram figure 3. typical filter and summing network 3 510 12 c c + mc1741 510 c c r1 2 r1 2 r1 2 r1 2 c r 2 ml12040 u d to vco 10 to 30v r 2 c r leads v (d output = ?? v leads r (d output = ?? r v lead lag
lan s dale s emiconductor, inc. ml12040 www.lansdale.com page 5 of 5 issue 0 p dip 14 = cp plastic package (ml12040cp) case 646?6 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m 10 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 outline dimensions lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili- ty, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical parameters which may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by the customer s technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc. plcc 20 = -4p ca s e 775-02 plastic package (ML12040-4P)
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